Bus priority has become an important component in advanced urban traffic control (UTC) systems. It improves the efficiency of bus services and hence encourages modal change to public transport. Currently a project for developing a Bus Information and Priority System (BIPS) is being undertaken by the Computer Systems Engineering Group (CSE) of University of Technology, Sydney (UTS) in conjunction with the Roads and Traffic Authority (RTA) of NSW and CSIRO. The main work of this project is to develop the above system (BIPS) as a subsystem of the Sydney Co-ordinated Adaptive Traffic System (SCATS) with the aim of giving bus priority at signalised intersections while having the minimum possible adverse effects on other traffic. BIPS will offer the capability of processing a group of buses competing for priority at related intersections. This will be achieved by optimising the signals at related intersections with a cost function which combines the total bus delay and stops at intersections. In this paper, the system architecture of BIPS is presented. (A)
Samenvatting